MOS technology requires a thin layer of dielectric material grown in the gate region to control induction of electric charge in the gate region to cause the flow of current through the device. Typically, the thin layer is a silicon dioxide (SiO.sub.2) layer, or silicon nitride (Si.sub.3 N.sub.4), or silicon oxynitride (SiO.sub.x N.sub.y) layer which is formed on the silicon substrate to function as a dielectric layer. The thin layer of silicon dioxide, or silicon nitride, or silicon oxynitride may also function as the dielectric material in fabricating capacitors in integrated circuits. The gate region blocks the flow of current in accordance with the applied voltage. In a reversed bias state, i.e. at cutoff, there exists a small amount of drain leakage current. The leakage current, even in the range of 1 amp per cm.sup.2 can be significant for CMOS devices in flash memory or logic applications. These CMOS devices will require the use of high dielectric constant material to prevent leakage currents, typically a dielectric constant in the 25 to 80 range. Material layers of silicon dioxide, or silicon oxynitride, will not provide the gate leakage current requirements for future products since their dielectric constant is in the 3 to 8 range. Known insulating material having a dielectric constant in the 25 to 80 range include tantalum pentoxide (Ta.sub.2 O.sub.5) and titanium dioxide (TiO.sub.2.). (Note: Of these two materials, tantalum pentoxide is the preferred insulating material, thus, the specification will specifically discuss the preferred use of tantalum pentoxide and will generally refer to the titanium dioxide or, other high dielectric constant insulating material, where required.) Tantalum pentoxide cannot be deposited directly onto the silicon substrate because of undesirable chemical reaction with the silicon substrate. A solution to the reaction problem is to fabricate a reaction barrier between the tantalum pentoxide and the underlying silicon substrate. The known reaction barriers include using silicon dioxide, or silicon nitride underlying the tantalum pentoxide or the other chemical reaction causing insulating material. The silicon dioxide (SiO.sub.2) layer, while effective as a reaction barrier, adds to the thickness of the total dielectric eliminating the advantage of the Ta.sub.2 O.sub.5. As taught in an article entitled: "Ammonia (NH.sub.3) Anneal of Silicon Surface to Prevent Reaction During Deposition/Formation of Tantalum Pentoxide", by Takahashi, p. 839, IEDM 1994, ammonia is used to form a silicon nitride barrier layer. The ammonia, however adds hydrogen to the interface of the device which causes unfavorable and unstable device characteristics.
To applicant's knowledge, a silicon oxynitride layer has not been formed using a pre-deposition anneal in nitric oxide (NO). A silicon oxynitride layer formed using a pre-deposition anneal in nitric oxide (NO) would not only be a reaction barrier for depositing the tantalum pentoxide dielectric, but would be hydrogen free, would be formed at a lower temperature than the ammonia, and could be alone as a dielectric layer in applications that do not require the stringent off-state leakage current requirements.
Thus, a primary object of the present invention is to provide a microelectronic integrated circuit substrate having a low gate leakage current characteristics (10.sup.-2 amps per cm.sup.2) facilitated by an insulating material layer, having a dielectric constant in the range of 25 to 80, and a silicon oxynitride reaction barrier formed using a pre-deposition anneal in nitric oxide (NO) process.
A particular object of the present invention is to provide a microelectronic integrated circuit substrate having a low gate leakage current characteristics (10.sup.-2 amps per cm.sup.2) facilitated by a tantalum pentoxide layer and a silicon oxynitride reaction barrier formed using a pre-deposition anneal in nitric oxide (NO) process.
A related object is to provide a fabrication process for producing a microelectronic integrated circuit substrate having a tantalum pentoxide layer and a silicon oxynitride reaction barrier without hydrogen, in accordance with the foregoing primary object.
Another related object is to provide a fabrication process for producing a microelectronic integrated circuit substrate having a silicon oxynitride isolation layer formed in accordance with the foregoing primary object and useable for other than as a reaction barrier layer.